Software for calculating PLL registers in LMX2306
LMX2306 is a very powerful PLL since is has one internal synthesisers.
The circuit has 3 registers which must be filled with data to work properly.
How to program LMX2306
The LMX2306 has 3 internal regist that must be set to make it work.
All transfer are 21-bit long.
The simplified block diagram below shows the R Counter, N Counter, and a Function Register.
The data stream is shifted (on the rising edge of LE) into the DATA input, MSB first.
The last two bits (yellow box) are the register selection control bits.
Below you will find the reference divider. This register is selected when the C2 and C1
are 0, 0. (yellow boxes)
By putting a divider value into the green area you will set the reference frequency.
Example: You have a reference crystal of 12.8MHz.
If you set the R-register (green) to divide with 1000 equal to 03e8 hex, the reference
frequency will be 12.8e6 / 1000 = 12800 Hz.
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Below you will find the divider register. This register is selected when the C2 and C1
are 0, 1. (yellow boxes)
This register contains two parts. N part (red) and Z part (blue).
The formula below the figure shows you how to calculate the VCO frequency.
I think an example will help you understand.
Let's say we want the VCO frequency to be 35.008MHz.
Earlier we set the Reference frequency to 12800Hz, which is the Fosc/R part
So we need to find out N part and Z part.
If i divid 35.008e6 / 12800 I get 2735.
So, 8*N + Z should be 2735. This gives me that N = 341 and Z = 7
One important thing about Z register is that 0 =< Z <= 7
Let's see if we got it right:
Fvco = [(8*341)+7] * 12800 gives 35.008MHz, Great!
PROGRAMMABLE DIVIDER (N COUNTER)
Below you will find the function register. This register is selected when the C2 and C1
are 1, 0. (Yellow boxes)
In the function register you can set many parameters, but I will only show you how to
set it make the circuit work in a simple way.
Three bits F3-F1 (blue boxes) set the output
test pin Fo/LD.
How the software works
Well I Let the R counter iterate from 650 to 1100. This means that the reference frequency will go from Xtal/1100 to Xtal/650.
Now when we have the reference frequency we divide the wanted frequency and see what the N Counter will be.
Example:
12.8MHz reference and 35.008 MHz.
Now R counter will start by dividing the Xtal (12.8MHz) by 650 = 12.8e6/650=19692.30769 Hz
We want 35.008 MHz so, the N Counter register should be 35.008e6/19692.30769 = 1777.75
The N Counter register can only hold an integer number and we didn't get one, the match is not perfect.
How much error do we have?
Closest integer number is 1778 so the frequency will be 17778*19692.30769= 35.012923 MHz
The error is 35.012923 - 35.008 = +4923 Hz which was not so good result.
The software then jumps back and make same calculations but the R counter register is now increased by one (651). This keep repeating until I reach 1100.
The best results with lowest error will then be presented.
